Sr. Digital Design Verification Engineer



As a Senior Verification Engineer you will be working on the verification and test system development of advanced CMOS Image Sensors. You will join a team that works with the design of timing and control signals for CMOS pixel array readout, analog/digital converters, as well as serial and parallel I/O interfaces for use in OVT’s Image Sensors, which also include ISP functions such as black level compensation (BLC), defect pixel correction (DPC), lens correction, and high dynamic range processing.


  • Image sensor control and processing function verification
  • High speed interface (MIPI) verification
  • Full-chip verification
  • Test system development & automation
  • Chip bring-up, validation, and debug
  • FPGA emulation bring-up and verification
  • Test procedures and test report documentation
  • Opportunity to grow into a technical and/or management lead role


  • Must have: Minimum MSEE + at least 4 yrs. OR BSEE + at least 6 years of digital design experience
  • Must be: Familiar with digital design flow, including RTL coding/simulation, and formality
  • Knowledge of FPGA and emulation platforms
  • Knowledge of assertion-based formal verification
  • Knowledge of scripting languages; e.g., Python, Ruby
  • Knowledge of Verilog, System Verilog, C/C++
  • Knowledge of ASIL is a plus
  • Image processing/DSP knowledge is a plus
  • excellent command of English as a working language