CPU/SOC Power Analysis & Optimization Engineer
Description
Ventana Micro Systems is at the forefront of the two hottest trends that are revolutionizing the semiconductor industry: RISC-V and Chiplet Architecture. Check out our CEO talking with global tech analyst Patrick Moorhead about how Ventana combines the extensibility of RISC-V with chiplet technology to create customer-driven innovation for best-in-class solutions for the data center.
Ventana is well-funded and backed by some of the largest strategic investors in the industry with the goal of building best-in-class CPU cores for cloud, enterprise, 5G, and Edge computing. We invite you to join the revolution and contribute to one of the Hottest Semiconductor startups in the industry.
CPU/SOC Power Analysis & Optimization Engineer:
For this role, the candidate must have strong analytical skills and background in power, micro-architecture and scripting to support the following activities on CPU, Compute Subsystem, and SOC designs:
- Characterization and development of dynamic power estimation and management features
- Develop energy models for early power estimation, what-if analysis and power targets
- Support RTL and gate-level power rollup and analysis
- Analyze various workloads to identify power reduction opportunities
- Evaluate, evangelize, and implement power optimizations in both RTL and gates
- Identify best power sign-off tests to improve power analysis coverage
- Develop flows & heuristics to accelerate power triage on large power data sets
- Present power results on a regular basis
Qualifications Required:
- 8+ years industry experience with high performance CPU or GPU, memory subsystem, or related system-level designs
- Bachelors or Masters degree in related engineering field
- Strong domain knowledge of computer architecture
- Knowledge of low power ASIC design and implementation techniques
- Ability to work independently and across geographies
- Excellent communication skills, self-motivated and well organized
Skills Desired:
- Verilog/SystemVerilog development experience
- Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems
- Experience with a broad range high frequency design considerations (timing, multiple clock domains, clock distribution) including power.
- Experience with typical front-end tools including: Verilog simulators, waveform viewers, and linting tools, as well as logic synthesis and place and route
- Experience in compiled and/or interpreted (Python, perl) languages
- Experience in product level power budgeting and projection
- Experience in Joules, PowerArtist, PTPX or similar power analysis tools
- Experience in data mining applications to power modeling & triage
- Experience in power use-case definition and analysis
- Experience in post-silicon power correlation is a plus
- Experience in power management techniques is a plus
BASE SALARY RANGE
$115,000 TO $268,000 per year
EEOE
Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law.
COVID-19
Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/ business partners.
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