Process Assembly Design Kit (PADK) Development

UEC/AEL San Jose, California


Description

Job Title: Process Assembly Design (PADK) Development 
Office Location: San Jose, CA
Work Model: Onsite
       
At SK hynix America, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix America, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.
Responsibilities:
  • Lead Process Assembly Design Kit (PADK) development and implementation for advanced packaging technologies
  • Provide advanced packaging physical verification flow by driving advanced package design and sign off flow development
  • Bridge internal efforts with customers to validate advanced package design to optimize the device-package performance
  • Drive strategic R&D projects, developing advanced package design kits
     
Minimum Qualifications:      
  • MS in Electrical Engineering or equivalent industry experience
  • 5+ years of experiences in physical verification flow and methodology developments for silicon process technologies or advanced packaging
  • Working knowledge in DRC (design rule check), LVS (Layout versus schematic), and physical design layout tools
  • Effective communication skills
  • Experience working effectively with cross-functional teams
     
Preferred Qualifications:     
  • PhD in Electrical Engineering or equivalent industry experience
  • 7+ years of experiences in Physical verification flows and methodologies for silicon nodes or advanced packaging
  • Working knowledge in DRC (design rule check), LVS (Layout versus schematic), and physical design layout tools
  • Working knowledge on advanced package designs and signal & power integrity
  • Experiences of co-working with EDA partners for tool or new design validation flow developments
  • Effective communication skills
  • Experience working effectively with cross-functional teams
Total Rewards:       
  • Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. The U.S. pay range for this position is base $120,000 - $160,000. Pay within this range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.
    • Our benefits include:
      • Top Tier health insurance at no employee cost
      • Paid day offs: PTO + Company Holidays + Happy Fridays
      • Paid Parental Leave Program
      • 401k Matching
      • Educational reimbursement up to $10,000 per year
      • Donation Matching and volunteering opportunities
      • Corporate discount programs
      • Free Breakfast/Lunch/Dinner provided to employees
Equal Employment Opportunity:

SKHYA is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.