Machine Learning (ML) Design Verification Engineer

Engineering - Hardware San Jose, California


Description

MACHINE LEARNING DESIGN VERIFICATION ENGINEER - SAN JOSE

Location: San Jose, CA
Job AI2061

Job Description
As the Machine Learning Design Verification Engineer, you will participate in definition and develop the verification methodology for SiMa.ai’s MLSoC™. You will be responsible for developing test plans, test-benches (drivers, monitors and checkers/scoreboard etc.) and test cases. You will be executing test plans to verify the MLSoC functionality, performance and coverage analysis. You will work closely with the architecture, RTL/uArch, and cross-functional
teams.

Required Background

  • BS in Computer Science/EE with 8+ years of experience or MS in Computer Science/EE with 6+ years of experience in SoC design verification.
  • Experience with block level, cluster level or chip/SoC-level verification.
  • Proficiency in system verilog, UVM, constrained random and coverage driven verification methodology.
  • Experience with development of test bench components, test plans for IP verification.
  • Good system verilog programming, debug and problem solving skills.
  • Scripting languages, python or perl is a plus.

Desired Qualifications and Skills

  • Machine Learning (ML) and/or CPU verification experience.
  • C/C++.
Personal attributes: Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.