Physical Design Engineer
About Silicon Labs
We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives.
Why this position matters
The Internet of Things is a fast growing, innovative market. Silicon Labs has invested in several exciting and market-leading highly integrated mixed signal SoCs aimed at IoT. The low power Gecko MCUs and Wireless MCUs that we develop will be deployed in literally millions of products worldwide. The IoT is the future of Silicon Labs and the SoC Implementation team plays an important role in the realization of that future. As a Middle-End Design Engineer, you will work with our design team to define and deliver key flow’s and chip implementations within the low power wireless MCU platform.
Is this a great match for you?
It is if you are a highly motivated, self-driven, talented Engineer with demonstrated knowledge of the IC design flow, all the way from initial idea to implementation. Engineers inquiring about this position should be familiar with digital implementation tools with focus on middle-end implementation like, synthesis, logical-equivalence checks, low-power intent. Basic knowledge of place and route to support physical-aware synthesis is desired. Successful candidates will have excellent written and oral communication skills in English and will be comfortable explaining technical concepts to a wide range of audiences, including senior engineering leaders.
The candidate will be a technical contributor as part of a digital design team implementing highly integrated mixed signal SoC’s for IoT products, include MCU and Wireless SoCs, performing middle-end implementation using deep sub micron technology.
- Block and chip level synthesis, validating constraints to meet speed, area, power and test goals
- Block and chip level floorplanning
- Data preparation of IP, including analog macros, I/O’s, memories, libraries
- Detailed place and route for both block macros and chip level, including clock tree synthesis, power routing, timing driven placement and routing, signal integrity analysis, and design for yield techniques.
- Generation of detailed parasitic information
- Static and Dynamic rail analysis
- Signoff Static Timing Analysis
- Physical verification, including LVS and DRC
- MS in Electrical Engineering, or equivalent
- Minimum of four years of design experience
- Strong knowledge of engineering fundamentals
- Knowledge of System-On-Chip or ASIC design, and understanding of SoC or ASIC tools/flows
- Advanced design implementation skills: synthesis, floorplanning, clock tree synthesis, power routing and analysis, timing driven place and route, signal integrity analysis, parasitic generation, static timing analysis, physical verification
- Advanced knowledge of low power flows, including voltage/power domains, power shutoff, retention.
- Advanced knowledge of CMOS fabrication processes
- Understanding of design for test techniques, including scan insertion, ATPG, Memory BIST, JTAG
- Knowledge of scripting/language (perl, shell, tcl, python)
- Familiarity with Quality systems and procedures
- Excellent written and verbal communication skills
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.