Sr Staff ASIC Engineer – Physical Design Engineer

Engineering - Hardware San Jose, California


Description

Position at Samsung Semiconductor, Inc.

Job Title: Sr Staff ASIC Engineer – Physical Design Chip Lead

Overview:

High performance computing and networking have been going through rapid transformation due to the explosive growth in cloud datacenter and automotive electronics. This growth has been driving increasing needs for innovative and integrated SoC Design services and solutions. Samsung Foundry is expanding SoC Design Engineering to support this need in North America.

 

This position involves hands on technical expertise along with project / program management work. This candidate will be responsible for hierarchical full chip physical design (place-and-route) including partitioning, floor-planning, building on-chip PDN, SDC clean-up, parasitic extraction, power integrity (static and dynamic IR-drop analysis), power and signal EM analysis, physical verification (DRC, LVS and DFMs).

 

This position will work with customer on top / level chip design issues and mentor block level physical designers, interact with internal Samsung management and external customers.

This position needs a self-motivated person who is able to handle entire project / program management RTL to GDS / Netlist to GDS working with teams across the world, creating & keeping schedules, working with EDA and ASIC vendors, tracking action items and ensuring design is on track.

 

Job Responsibilities:

This position will be responsible for hierarchical full chip physical design (place-and-route) including partitioning, floor-planning, building on-chip PDN, SDC clean-up, parasitic extraction, power integrity (static and dynamic IR-drop analysis), power and signal EM analysis, physical verification (DRC, LVS and DFMs). You will be responsible for the chip-level floorplan, budgeting and partitioning, chip-level place and route as well as static/dynamic IR-drop analysis and EM analysis. You will also be responsible for chip-level physical verification and Samsung physical design methodology support for ASIC customers.

 

The successful candidate is expected to have:

  • Solid experience in hierarchical physical design methodologies, especially big die implementation
  • Solid Experience in project/program management of ASIC and an understanding of RTL, Synthesis, DFT, Design Verification, Physical Design, STA, Physical Verification, Package, Test, assembly, etc
  • Solid experience in high speed CTS, timing closure on highly complex SoC
  • Solid experience in using place and route tools and achieving the best PPA of the full-chip physical design
  • Solid experience with advanced nodes like 7nm
  • Solid knowledge of NOC (Network on Chip from Netspeed/Arteris) Physical Implementation
  • Solid experience of working closely with STA and logic design engineers to close timing
  • Solid experience in PDN build and power integrity analysis flow (static/dynamic IR-drop analysis)
  • Solid experience in EM analysis and fix
  • Solid experience in physical verification flow including DRC, LVS, PERC and DFM rule checking and fix
  • Project / Program Management of ASIC from RTL to Packaged Part
  • Static Timing Analysis / Writing Timing Constraints
  • Chip-level physical verification / Static/dynamic IR-drop analysis and EM analysis

Required Skills:

  • BS or BE minimum with at least 10 years of additional industry experience.
  • Direct experience in ASIC or SoC design, with significant hands on experience in synthesis, low power, LEC, CLP, on hierarchical large complex projects.  Strong knowledge in clock distribution architecture and timing constraints development.
  • Comfortable working with and managing 3rd party teams.
  • Scripting languages (Tcl, Perl, Python), Documents Word processing, Power Points), Spreadsheet, email;
  • Highly passionate and energetic.
  • Excellent communication with RTL and physical design engineers.
  • Frequent customer and partner visits. Domestic and international travel.

 

Preferred Skills:

  • MS/PhD preferred.
  • Experience working on complex designs with NOC (Network on chip) from Netspeed or Arteris
  • Experience working on Networking , Data Center large die designs

 

#LI-RL1

 

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Samsung Semiconductor Inc. (SSI), an equal opportunity employer, is a world leader in Memory, System LSI, and LCD technologies. Headquartered in San Jose, California, SSI is a wholly-owned U.S. subsidiary of Samsung Electronics Co., Ltd.- the second largest semiconductor manufacturer in the world and the industry's volume and technology leader in DRAM, NAND Flash, SSDs, mobile DRAM and graphics memory. It is one of the largest providers of system logic, imaging and LED lighting solutions, as well as providing advanced process design and manufacturing for fabless companies. Samsung Semiconductor, Inc. also has a research and innovation center with numerous labs providing product design and research in: logic, memory, image sensors, displays and mobile technologies. In addition, the company supports Samsung Display Company, the largest producer of LCD and OLED displays.

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