Mixed Signal IC Verification Engineer

IC Design Engineering San Jose, California


Digital/Mixed Signal IC Verification Engineer

San Jose, CA



  • Develop SystemVerilog/Verilog-AMS models for analog circuits and circuit blocks to enable efficient full chip functional verification.
  • Create block and chip level testbenches using UVM/SystemVerilog environment
  • Participate in design verification by performing schematic/behavioral comparisons, writing assertions and debugging code
  • Develop verification environment, including all the respective components such as stimulus, checkers, assertions and coverage
  • Work with designers to develop verification plans
  • Execute verification plans, bring up DV environment, do regression testing, debug failures
  • Help with post-silicon debug and correlation



  • BS or MS in EE and/or Computer Science
  • Minimum of 3 years of experience
  • Deep understanding of event driven simulator modeling techniques
  • Strong knowledge of mixed-signal concepts and digital-analog interface
  • Proficient in Verilog, SystemVerilog and Verilog-AMS HDL
  • Deep understanding of real, wreal, EENET and user-defined-type data structures
  • Good background in circuit design to understand transistor-level schematics and analyze verification results
  • Experience developing scalable and portable test-benches
  • Experience with mixed signal verification methodology
  • Experience in UVM or equivalent SystemVerilog object oriented verification methodology is highly desired
  • Experience with one of the scripting languages: Python, Perl, TCL