Senior Failure Analysis Engineer
Description
Job Description:
The Senior Failure Analysis Engineer will perform IC level failure analysis to support RMA and internal/external customer issues.
Job responsibilities include, but are not limited to, the following.
• Performing fault isolation and defect analysis/characterization on power IC’s to identify root causes of product failures in power supply applications and/or in production test.
• Provide comprehensive technical reports to customers on findings from product failure investigations.
• Provide corrective actions to internal and external customers based on the results of the analysis.
• Visit customers as necessary to resolve customer satisfaction issues arising from any quality problems and/or customers' perceptions about PI quality.
• Provide support to Power Integrations customers in Asia on quality problem resolution to ensure customer satisfaction. This person will act as a liaison between the factory and the customers on matters of resolving customers’ production and field quality problems, thereby promoting PI’s quality value.
• Responsibility will also include effective verbal and written communication of results, which will be used to drive improvements in product design, process technology, and applications. Such communication will require, but not limited to, writing cogent and convincing technical reports suitable for external customers.
Experience & Requirements:
• Candidates with background and experience in automotive failure analysis/customer communication will be given preference.
• Good verbal and technical writing skill in English is required.
• Minimum of 5 years of experience in failure analysis of power semiconductors, analog, and/or mixed signal IC devices.
• Hands-on experience in failure analysis, and electrical fault isolation and defect characterization tools and techniques such as the following: ATE, curve trace, nano/micro-probing, OBIRCH/EMMI microscopy, liquid crystal, CSAM, XRAY, FIB, SEM/EDX and manual cross-sectioning and deprocessing techniques using both parallel-polishing and wet chemical etch techniques.
• In-depth understanding of both digital and analog circuits, device physics and IC fabrication processes.
• Ability to interpret IC ATE test data log is required. Ability to interpret system level schematics, the IC level schematics, and IC layout of CMOS and bipolar devices is required.
• Fluent verbal and written communication skills in Mandarin is required.
Education:
- Must have B.S. degree in electrical engineering.
- Candidates with MSEE will be given preference.