Design Verification Engineer

Engineering Santa Clara, California


Description

Our Mission

At Palo Alto Networks® everything starts and ends with our mission:

Being the cybersecurity partner of choice, protecting our digital way of life.

We have the vision of a world where each day is safer and more secure than the one before. These aren’t easy goals to accomplish – but we’re not here for easy. We’re here for better. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are.

Your Career

We are looking for an ambitious, team senior networking FPGA and ASIC verification engineer to participate in the verification effort. You will be a key member of the FPGA and ASIC system, full chip, and block level verification team. Your responsibilities will include developing the verification environment; developing test plans and verifying the function of the FPGA and ASIC.

Your Impact

  • Hands-on implementation work for every aspect of FPGA and ASIC verification, working closely with the system group, architects, RTL designers, and verification teams
  • Developing the verification flow and methodology, testbench and test cases, plus executing the test plan, working closely with the design team to ensure the highest design quality
  • Debug test failures at a block, full chip, and system level
  • Evaluate and enhance test plans to increase test coverage
  • Run regression
  • Have a full understanding of design using Verilog, and working experience with C/C++

Your Experience

  • BS EE, CE or CS; or equivalent work experience required, MSEE preferred
  • Minimum of 3-4 years of FPGA and ASIC design verification experience with a proven track record of successfully verifying and delivering complex FPGAs and ASIC
  • Experience in going through several complete and successful FPGA design/verification cycles from architecting and creation of FPGA and ASIC test environment to tape-out and post-silicon validation is required
  • Strong leadership/communication/interpersonal skills required
  • Proven track record in the following areas of DV required:
  • Test bench design and implementation
  • Test plan definition
  • Constrained random test development
  • Coverage specification and analysis
  • Reference model design and implementation
  • Automation of the regression test suite
  • Solid technical skills in the area of design verification
  • Strong object-oriented software design and programming skills in C/C++
  • SystemVerilog, OVM, UVM is required
  • Experience with UVM is highly desirable
  • Solid verification skills: planning, problem-solving, debugging, random testing, adversarial testing required
  • Experience in formal verification desired

The Team

Our engineering team is at the core of our products – connected directly to the mission of preventing cyberattacks. We are constantly innovating – challenging the way we, and the industry, think about cybersecurity. Our engineers don’t shy away from building products to solve problems no one has pursued before.

We define the industry, instead of waiting for directions. We need individuals who feel comfortable in ambiguity, excited by the prospect of a challenge, and empowered by the unknown risks facing our everyday lives that are only enabled by a secure digital environment. 

Our Commitment

We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.


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