Senior Layout Design Engineer
We are looking for qualified CMOS Image Sensor layout engineer with expertise in custom layout integration and verification of a mixed signal IC. The qualified candidate should have deep understanding of analog block layout techniques, chip floor planning, physical verification including LVS, DRC, ERC, Antenna rule check etc.
- Lead full-custom IC layout design and verification, including chip floorplanning, analog IP layout and chip level layout integration of various analog, mixed signal and ASIC blocks.
- Translate hierarchical schematics into layout with DRC, LVS, ANT, ERC soft-check clean.
- Layout schedule planning and working with other IP layout engineers to integrate various layout blocks.
- Assist with tight tape-out schedules if needed.
- BSEE with at least 6 years of experience in analog IC full-custom layout.
- Tool experience using Cadence Virtuoso, Mentor Calibre LVS DRC ERC soft-check; Cadence Assura and PVS verification a plus.
- Experience working with 22nm/40nm process nodes.
- Prior image sensor layout experience is a huge plus.
- Knowledge in device matching, balance, and shielding of critical device and signal.
- Layout skills to finish tasks quickly, and help project lead with tape-out schedule planning.