Digital Design Engineer

ENGINEERING Santa Clara, California


  1. Participate in chip level architecture definition, including ISP datapath, power consumption and performance;
  2. RTL design and verification of digital circuit for CMOS Image Sensors, such as the design of timing and control signals for CMOS pixel-array readout in multiple clock domains, analog/digital converters, high-speed I/O interfaces (MIPI, LVDS and SPI);
  3. Developing Image-Signal-Processing (ISP) functions, such as black level compensation (BLC), defect pixel correction (DPC), AWB Gain, PD Compensation, Median Filter, Deep Noise Suppression (DNS), Lens Correction and high dynamic range (HDR) processing;
  4. Performing full-chip integration, Logic Synthesis, Logic Equivalence Checking, Static Timing Analysis, Power Consumption Analysis and Post Simulation;
  5. Cooperating with the Physical design team to fix timing violation and issues of P&R and DFT;
  6. Cooperating with other teams to debug the functionality and optimize the performance of fabricated image sensor chips;
  7. Perform digital ECO based on needs.

MS degree in Electrical Engineering and 2 years of research or work experience in ASIC/digital-circuit design; clock domain crossing; asynchronous/synchronous IPs; hardware language (Verilog, SystemVerilog), script language (Python, Perl), C/C++, Matlab;  Design Compiler, PrimeTime, PTPX, and Formality; physical design tools Virtuoso (Schematic/Layout Editor); Hspice; Power Supply, Function generator, Oscilloscope and Welding Machine.