System-On-Chip Modeling Engineer (Staff/Sr.Staff)

CTO OFFICE Santa Clara, California


Description

        As System-on-Chip Modeling Engineer in the Office of the CTO at OmniVision (OVT), you will be responsible for system level modeling and validation of next-generation imaging systems in order to understand system performance, derive specifications and analyze and overcome failure modes. The CTO office is responsible for identifying novel imaging technologies and defining the technology roadmap. The CTO office is looking for someone self-driven and eager to learn.

 Responsibilities:

  • Model new image sensor technology System-on-Chip solutions using Python/SystemC/VerilogA. Emphasis, here, is on model development of analog and mixed-signal pixel circuitry and readout circuitry in order to enable efficient system emulation suitable to generate e.g. training data for early algorithm development
  • Validate and match system level models against circuit simulations and real world performance and draw conclusions
  • Engage closely with cross-functional teams including Design, Algorithm, and Application Engineering to establish and validate important system parameters and their trade-offs
  • Define system specifications and analyze failure modes
  • Identify potential solutions to overcome circuit/device limitations at early R&D stage
  • Assist in product planning by careful balance of schedule, resources and key specifications

 Qualifications: 

  • MS or PhD in electrical engineering, computer engineering or related fields or equivalent combination of education and experience. PhD is a plus.
  • Strong background in electrical engineering, IC design, Analog design, Mixed Signal design required
  • Experienced in CMOS image sensors, camera systems, image signal processing and/or digital signal processing or related fields preferred.
  • Experienced in using Cadence/Virtuoso in the context of SPICE/Spectre circuit simulations required. Experience in Skill/Ocean scripting languages preferred.
  • Experienced in Python Experience in SystemC and VerilogA strongly preferred. Familiarity with C/C++ in an object-oriented context is a plus
  • Excellent verbal, written and communications skills required

EOE/Minorities/Females/Vet/Disability