Senior/Staff CIS Array Design & Layout Engineer
We are looking for qualified CIS array design & layout engineer with deep understanding of CIS array layout, deep understanding of analog layout and good understanding of analog circuit to layout, integrate and simulate various blocks used in the pixel array and readout circuits of CMOS image sensors. Candidate should have the capability to do block layout, layout integration, simulate and analyze performance of array cell of image sensor, as well as experience in debugging/verifying design issues.
As Senior/Staff CIS Array Design & Layout Engineer you will:
- Lead and work on detailed transistor level layout of high performance analog and mixed signal circuits for CMOS image sensors especially pixel array, column readout circuits, row decoders, line memory, etc
- Perform the block level and transistor level layout design, floor planning and optimization of sensor array readout circuits using CAD tools like Cadence Virtuoso and Calibre.
- Collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors and help to successfully bring new products from initial concept through release.
- Propose innovative and creative solutions where necessary to meet customer needs.
- Instruct less experienced engineers when necessary.
- Must have experience in pixel layout and sensitive analog circuits.
- Must have knowledge of analog circuit and semiconductor device physics.
- Good communication skills and ability to document, present the designs for review.
- Experience/knowledge in CMOS image sensor readout circuit design is a plus.
- Experience/knowledge in image sensor and camera system is a plus.
- Minimum of 6 plus years of relevant experience.
- MSEE or equivalent.