Senior / Lead CMP Process Engineer
- Process owner for Chemical Mechanical Planarization (CMP) process.
- Sustain and improve daily operations in CMP process to meet module goals in quality, yield, cost and productivity improvements.
- Work closely with NPI to support new products qualification and process characterization in CMP.
- Establishing good process margins and inline controls of these new processes. Creating and updating of process specification and documentation of working procedure.
- Implement SPC improvements and early fault detection systems for CMP.
- Resolving reliability or yield issues related to the CMP processes and lead trouble-shooting of defect yield issues and process excursions associated with the new process/tools.
- Establish Out-of-control Action Plans, specifications for procedures to be followed.
- Provide training to engineering technicians and production personnel.
- Any other duties assigned by the manager.
• B.S. Degree in Microelectronics, Chemical Engineering, Materials Science, Chemistry, Solid State Physics or other relevant engineering physical science discipline is required.
• Minimum of 5 years of Semiconductor process engineering experience in CMP related processes preferably in 8” or 12” wafer fab and experience with AMAT MIRRA MESSA tools is an added advantage.
• Minimum of 5 years’ experience with design of experiment techniques (DOE), Statistical Process Control (SPC), Defect analysis and data analysis.
• Self-driven leader and strong team player with keen technical ability, systematic approach, detailed-oriented, excellent problem-solving skills, and positive attitude
• Good interpersonal and analytical skills.
• Ability to work independently, be hands-on and expected to dive into technical details as required.