System HW Engineer, Intern

Engineering Pavia, Italy


Inphi Job Specification

Intern System HW Engineer



Inphi Corporation, a high-speed analog/mixed-signal semiconductor company, is the market leader in high-speed and optical interconnects for communication infrastructure in long-haul, metro and datacenter. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center from 10Gig to multi-hundred-Gig (> 100G) network environments. By leveraging our core competencies in advanced analog circuit design, advanced DSP (Digital Signal Processing), packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi is publicly traded on NYSE under the symbol “IPHI.”


Our innovative approaches have resulted in the company’s products being first to market in many of key areas, including opto-electronics and DSP based transceivers providing most advanced chips and subsystems solutions to address today’s and future’s multi-100Gig interconnect requirements for the ever-increasing demand of higher data rates. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.




As a Intern HW Engineer for the Communication System Hardware team in Pavia, Italy you will be joining a growing team responsible for the Hardware and Software algorithm needed for characterization and validation of the physical layer of high frequency SerDes systems, Optical modules, DSP based communication systems and other key chips developed by the company.


You will be supporting validation lean in defining testing architecture, support the HW EVB needs, validation plans and the development team during debug phase. Few specific projects focusing in the following areas are available

1-              Low level control board drivers and implementation

2.              perform validation of specific high frequency analog blocks

3.              Design of validation boards companion PCB (control – power)

4.              Development of validation SW infrastructure components (Data Management/ GUI / Instruments automation)

5.              Design of high frequency PCB


After internship as a future Application Engineer you’ll be responsible of:


              Support design team in HW and SW debug

              Coding and set up of manual and automatic characterization routines

              Support in validation of HW blocks (PLL, ADC, DAC…)

              Support design/simulate/and debug of characterization/evaluation boards

              Responsible for detailed experimental verification (HW and SW level) and characterization reports

              Involved in architecting and deliver demos to technology capability

              Work with the team in facing direct problems coming from customer application

              Work with IP teams and customers to ensure proper usage of the eSilicon SerDes for various applications and protocols



Experience requirements Include:

              Completion of Junior (3rd year) student enrolled in a Bachelors in CS/EE

              Experience in Perl, Python, C/C++ and TCL

              Familiarity with FPGA design flows is a plus

              Familiarity with high-bandwidth oscilloscopes, BERTs is a plus

              Strong written and verbal skills


Characteristics being developed during the internship period:

              High frequency lab equipment and their interface (Sampling scopes, Signal generators, PNA, Spectru, BERT)

              Lab automation and automation scripts

              Data logging and data tools for validation reports

              SerDes architecture

              SerDes programming and proper use in multiple use case

              Firmware main routines for SerDes testing


Only those who meet the qualifications described herein will be considered.

Candidate must be eligible to work in country of hire without restrictions.