SOC DESIGN VERIFICATION ENGINEER
Description
Esperanto delivers high-performance, energy-efficient, and innovative computing solutions that are the compelling choice for the most demanding AI and non-AI applications. The changing, computationally intensive workloads of the machine learning era mandate a new clean-sheet solution, without the baggage of existing legacy architectures, or the programmability limitations of overspecialized hardware. Esperanto leverages the simple, elegant, open standard RISC-V ISA along with leading-edge system architectures to deliver flexibility, scalability, performance, and energy-efficiency advantages.
Responsibilities
-Create verification content including testplans, test bench components, directed and constrained random
tests, and functional coverage
-Execute testplans to fully verify SoC component blocks
-Broader responsibilities may include supporting full-chip simulation, emulation, and post-silicon bring up
Qualifications
- Ability to clearly communicate across teams with multidisciplinary backgrounds
- 5+ years of experience in CPU, IP or SoC verification
- Knowledge of high-level verification flow methodology (testplan development, constrained
random test generation and debug, coverage analysis and closure)
- Experience with a class-based testbench using System Verilog is required
- Knowledge of processors, cache, and cache coherence is required
- Experience with UVM/OVM is required
- BS/MS EE
Nice to Have
- Experience with Tcl is a plus
- Experience with C and RISC-V assembly programming is a plus
- Experience with Python, Perl, or other scripting languages is a plus
Benefits
- Base salary range is $100,000 - $300,000
- You will also be eligible for stock options, healthcare and other benefits
The actual salary of a successful applicant may vary from the posted range based on a candidate’s experience, training, education, location and/or other legitimate business reasons