Principal Engineer – RTL Design
Description
Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, our innovative microinverter technology revolutionized solar power, making it a safer, more reliable, and scalable energy source. Today, the Enphase Energy System enables users to make, use, save, and sell their own power. Enphase is also one of the most successful and innovative clean energy companies in the world, with more than 80 million products shipped across 160 countries.
Join our dynamic teams designing and developing next-gen energy technologies and help drive a sustainable future!
Join our dynamic teams designing and developing next-gen energy technologies and help drive a sustainable future!
About the Role
Enphase is seeking a highly skilled and experienced Senior RTL Design Engineer to join our ASIC Engineering team in Fremont, CA, to design next-generation controllers for power conversion and power line communication. The team is currently developing advanced 22nm ASICs that will serve as the core of future solar inverters, batteries, and bi-directional chargers. In this role, you will contribute to the design and optimization of custom IPs, implement complex digital circuits, and play a key role in pre-silicon validation using FPGAs for early functional verification and system-level debugging. The ideal candidate will have a proven track record of successfully driving ASIC projects from concept through tape-out and into production.
Enphase is seeking a highly skilled and experienced Senior RTL Design Engineer to join our ASIC Engineering team in Fremont, CA, to design next-generation controllers for power conversion and power line communication. The team is currently developing advanced 22nm ASICs that will serve as the core of future solar inverters, batteries, and bi-directional chargers. In this role, you will contribute to the design and optimization of custom IPs, implement complex digital circuits, and play a key role in pre-silicon validation using FPGAs for early functional verification and system-level debugging. The ideal candidate will have a proven track record of successfully driving ASIC projects from concept through tape-out and into production.
What you will do
- Microarchitecture: Start with requirements document and come up with detailed logic implementation
- Work closely with the architecture & modelling teams to coordinate the development of ASIC IP development & system level models.
- RTL Design and Development: Design, implement, and optimize RTL (Register-Transfer Level) for digital logic blocks and sub-systems, ensuring they meet architectural, performance, and power requirements for a 22 nm process node.
- ASIC Design Flow: Lead and contribute to all phases of the ASIC design flow, including micro-architecture, RTL coding in Verilog, linting, clock domain crossing (CDC) analysis, synthesis, and static timing analysis (STA).
- FPGA-Based Pre-Silicon Validation:
- Adapt ASIC RTL for FPGA synthesis, addressing differences in clocking, memory, and I/O structures.
- Help subject matter experts perform pre-silicon validation and debugging of the ASIC design on a large-scale FPGA prototyping platform.
- Collaborate with the software and firmware teams to enable early software development and system-level validation on the FPGA prototype.
- Verification and Debugging: Work closely with the verification team to define test plans, review coverage, and debug complex functional and performance issues.
- Collaboration and Documentation: Participate in design reviews, create detailed design specifications, and provide technical leadership and mentorship to junior engineers.
Who you are and What you bring
Education and Experience
Education and Experience
- Bachelor's or master’s degree in electrical engineering, Computer Engineering, or a related field.
- 15+ years of experience in RTL design for ASIC development.
- Demonstrated experience with sub-28 nm process nodes, with specific knowledge of 22 nm design considerations.
- Proven experience in pre-silicon validation using FPGAs for complex ASIC designs.
Technical Skills
- Expertise in Hardware Description Languages (Verilog).
- Familiarity with one or more of NL5, C, Python, Matlab based modelling/simulation environments
- Strong understanding of the ASIC design flow, from specification to tape-out
- Strong proficiency with EDA tools for simulation (Synopsys VCS, Cadence Incisive), synthesis (Synopsys Design Compiler), and static timing analysis (Synopsys PrimeTime).
- Hands-on experience with FPGA synthesis and implementation tools from vendors like Xilinx or Intel/Altera (e.g., Vivado, Quartus).
- Proficiency in scripting languages such as Python, Perl, or Tcl for design automation and flow development.
Preferred Qualifications
- Experience with processor architecture (e.g., ARM, RISC-V) and SoC integration.
- Knowledge of advanced low-power design methodologies, including multi-voltage domains, clock gating, power gating and dynamic voltage scaling.
- Experience with advanced verification methodologies such as UVM.
- Familiarity with formal verification techniques and tools (e.g., Synopsys Formality).
- Prior experience in a leadership or mentorship role.
Personal Attributes
- Strong problem-solving and analytical skills.
- Excellent communication and teamwork abilities.
- Detail-oriented and highly organized.
- Ability to work in a fast-paced, collaborative environment.
The base pay range for this position is $160,000 to $226,800. This salary range may be modified in the future. The successful candidate’s starting pay will be determined based on relevant skills, experience, education or training, work location, and market conditions. This position is also eligible for generous stock, bonus, and benefits.