Sr. Principal Design (Physical & Synthesis )
SoC Integration lead
Enphase is looking for experienced SoC design engineers with SoC Logic Integration, Synthesis & STA closure experience to join our newly formed team in Bangalore India. The team is being formed to bring our next generation Control ASIC to production in 22nm technology. The ASIC will be a Mixed Signal SOC built around ARM microcontrollers.
This position is in our ASIC Engineering Team Reporting to the Senior Director of ASIC Engineering in Bangalore India.
Own full-chip RTL integration to Synthesized netlist generation. Act as liaison with our ASIC backend design services partner. You will be working with the Architecture & IP design teams for RTL Integration, timing constraints creation, synthesis. You will also validate the STA results on the final database delivered by our ASIC partner.
Deep understanding and experience in SoC architecture and integration
Ability to create the timing constraints based on specification
RTL Integration of SoC/Subsystems from IPs, ability to debug the issues in logic verification, act as liaison between Design and Place and Route teams
Knowledge of all the Soft IP collateral and deliverables eg: Lint, CDC, Synthesis, Timing constraints, LEC & ATPG
Experience and ability to bring complex SOCs into the physical world and into production
#SoC Integration #ARM #Synthesis #Timing Constraints #STA #DFT
This position is based in Bangalore
Prior hands on work experience of 8-15 years in SoC design.