Fall Co-Op - Mixed Signal Modeling and Verification Engineer BM-5976

Students and Graduates Mesa, Arizona

We are seeking a creative and hardworking fall co-op to join our outstanding Analog/Mixed-Signal Verification team. You will collaborate with systems and design teams to facilitate top down design methodology. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. This position will play a vital role streamlining development methodology for our organization. We are proud of our outstanding environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!

Responsibilities

  • You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs
  • Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS
  • Develop test plans, test benches, and verification methodologies to verify the microarchitecture and design
  • Independent Interpretation of analog circuit schematics into abstract models
  • Collaborate with system architects and designers to streamline architectural exploration of next-generation IP
  • Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow
  • Collaborate with multi-functional teams to streamline chip-level integration
  • Performing regression debug support and other flow/infrastructure development

Required Skills and Qualifications

  • Currently pursuing a MS or higher in Electrical Engineering or Computer Engineering
  • Strong background in System Verilog for real number modeling (RNM) modeling, test bench development & verification
  • Solid understanding and hands on experience on the design of mixed signal designs
  • Organized and detailed with strong communication skills
  • Possess outstanding analytical and problem-solving skills
  • Hard-working and ability to operate in dynamic environment
  • Strong knowledge of System Verilog RTL debug

Preferred Skills and Qualifications

  • Python skills would be highly desirable
  • Teaming closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post silicon validation efforts
  • Knowledge of signal processing and System Verilog Assertions and PSL Assertions
  • Ability to create, evaluate, debug, and improve a verification process
  • Opportunity to mentor junior engineers in verification methodology
  • UVM experience would be highly desirable
  • Prior experience with SDF annotation in AMS simulations
  • Prior experience with UPF or CPF

This position is located in Mesa, AZ

Cirrus Logic follows a 2+ day in-office work schedule but interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference. Interns must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning their internship with Cirrus Logic.

Cirrus Logic is an Equal Opportunity/Affirmative Action Employer. We strive to select the best qualified applicant for any opening and to reward employees based on their skills, experience and performance. We do not discriminate on the basis of race, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, genetic information or any other characteristic protected by law.

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