Physical Design Engineer SP-5690

Engineering Services Mesa, Arizona

Due to continued product line expansion, Cirrus logic is looking for a skilled Physical Design Engineer to join its Implementation team. You will be part of a team that is currently working on implementing industry-leading mixed-signal SoC for consumer mobile audio markets. This role would suit a candidate with an ability to work independently and as part of a wider design team.


  • You will be part of a close-knit team involved in all aspects of physical implementation from RTL to GDSII
  • Perform RTL synthesis and scan stitching
  • Applying deep knowledge of timing optimization and experience with ECO generation to analyze and fix timing issues in 40nm, 28nm and below
  • You will be defining and debugging Timing Constraints and performing STA using industry-standard STA engines and using a deep understanding of timing correlation, to achieve timing closure.
  • Build timing constraints for the entire chip in a team environment
  • Analyze power constraints and chip floor plan
  • Analyze clock distribution on full-chip assembly
  • Perform physical design-related flow development, tool evaluation, flow automation, QA and improvement.
  • Develop Placement & Route structures for a complete ASIC design
  • Build Static Timing Analysis, timing closure, ECO and tape-out
  • IR Drop analysis and improvement on almost all designs

Required Skills and Qualifications

  • Bachelor's in Electrical Engineering and 5+ or Master's in Electrical Engineering and 3+ years of proven experience in a Logic design or Physical Design position
  • Knowledge of automating and advancing flows using proficiency in Perl/Tcl scripting
  • Solid understanding of RTL design and the ideal candidate should be familiar with RTL compiler/Design Compiler, ICC/SOC Encounter
  • You will also have a working knowledge of scan insertion, and ATPG
  • Good communication and collaboration skills

Preferred Skills and Qualifications

  • You should have Primetime, Conformal LEC, and ATPG
  • Ability to perform debug/analysis skills for designs, library, and technology files
  • Ability to provide mentorship, guidance to junior engineers and be an effective teammate

This position is located in Mesa, AZ

This is a hybrid remote position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning employment with Cirrus Logic.

Cirrus Logic is an Equal Opportunity/Affirmative Action Employer. We strive to select the best qualified applicant for any opening and to reward employees based on their skills, experience and performance. We do not discriminate on the basis of race, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, genetic information or any other characteristic protected by law.