Digital Design Engineer (All Levels)

SoC San Jose, California



  • Integrate and validate PCIe IP in SSD SoCs
  • Work with designers from IP and SOC team to ensure PCIe functionality and performance meets specifications
  • Work with validation team on FPGA bring-up
  • Work with system team to support customer issue debug
  • Interface with PCIe IP vendors to ensure chip requirements are met



  • Bachelor of Science degree (MS preferred) in Electrical Engineering with a proven track record of product development to high volume production
  • More than 5 years of PCIe development experience
  • Hands on experience in PCIe RTL integration and simulation debug
  • In depth understanding of PCIe spec and TRANS/DLL/PHY layer design concept
  • Familiarity with AXI protocol
  • Familiarity with PCIe PIPE interface
  • Familiarity with PCIe FPGA bring-up


Desired Skills:

  • Experience working in a PCIe controller development team a plus
  • PCIe system debug experience a plus
  • PCIE PHY usage and debug experience a plus
  • Cadence/Synopsys PCIe IP experience a plus