Senior DDR Engineer

SoC San Jose, California


  • Lab experience with the bring up and validation of high speed DDR/LPDDR subsystem solutions
  • Experience with Cadence DDR Controller and PHY is a big plus
  • Knowledge about DDR4 and LPDDR4 JEDEC spec
  • Support the verification team with by developing verification strategies, debugging and providing coverage definitions
  • 8+ years of industry experience in the relevant field is required for this role