Digital ASIC Design Engineer

SoC San Jose, California


Working on RTL Design, supporting FPGA and verification activities of our next generation ECC IP and other key digital components for the SSD SoC. Interacting with Firmware engineers and System engineers to understand the requirements of the design components.

Skills Requirements:  

  • Logic Design, Simulation and Debugging
  • Verilog coding
  • Familiar with RTL design and verification flow such as lint and code coverage
  • Hands-on experience in at least one scripting language (Perl, Tcl, Python etc.)
  • Synthesis using Design Compiler or equivalent
  • FPGA design, debug and development experience is a plus
  • Error Correction Code background is a plus
  • C/C++ coding is a plus
  • SystemVerilog/UVM is a plus  


  • Bachelor or Master’s degree in EE or CE or related fields.
  • Good team player
  • Strong personal communication skills