Digital ASIC Design Engineer
- Working on RTL Design, supporting FPGA and verification activities of our next generation ECC IP and other key digital components for the SSD SoC.
- Interact with Firmware engineers and System engineers to understand the requirements of the design components.
- Bachelor or Master’s Degree in Electrical Engineering, Computer Engineering, or other related fields.
- Familiar with RTL design and verification flow such as lint and code coverage.
- Hands-on experience in at least one scripting language (Perl, Tcl, Python etc.).
- Logic Design, Simulation and Debugging.
- Verilog coding.
- Synthesis using Design Compiler or equivalent.
- FPGA design, debug and development experience is a plus.
- Error Correction Code background is a plus.
- SystemVerilog/UVM a plus.
- Good team player with strong communication skills.