Senior/Staff Digital Verification Engineer

Hardware Engineering Tai Seng, Singapore


Description

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world

           

We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance.


Summary:

The candidate will be an individual technical contributor as part of a digital design team developing highly integrated mixed signal SoC’s for the low power IoT products (MCU and Wireless).

 

Responsibilities:

  • Block and IP Verification
    • Verify IP blocks to validate performance and adherence to requirements in a reusable manner
    • Generate and execute verification plan
    • Determine and use of verification approach, such as directed, random, and assertion based methods
    • Coverage analysis
    • Define and implement random configurable verification models
    • Verification of mixed-signal and RF IP integration, including real-value modeling
  • SoC Integration and Verification
    • Integration of digital blocks/IP into the SoC infrastructure
    • Develop tests and testbenches for SoC integration with heavy emphasis on reuse
    • Gate simulations
    • C test development
  • Flows and Methodology
    • Improve flows and methodologies to streamline development and integration of IPs.


Requirements

  • MS in Electrical Engineering, or equivalent
  • At least four years of design and/or design verification experience.
  • Strong knowledge of engineering fundamentals
  • Knowledge of System-On-Chip or ASIC design, and understanding of SoC or ASIC tools/flows
  • Design/Verification skills
    • System Verilog, UVM
    • RTL Coding
    • System/IP modeling (Matlab, C, AMS)
    • Software/Firmware coding
    • Low-power implementation and verification (UPF, CPF)
    • System Verilog assertion and coverage analysis
  • Knowledge of scripting language (python, perl, shell, tcl)
  • Excellent written and verbal communication skills
  • Mentor junior engineers in UVM and verification fundamentals




We are an equal opportunity employer and value diversity at our company.  We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.