Sr. Staff SoC Hardware Architect

Engineering - Hardware San Jose, California


Position at Samsung Semiconductor, Inc.

Title: Sr. Staff SoC Hardware Architect 

Req ID#: DSA32834


The Technology Enabling and Development (TED) Lab is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash, and SRAM memory.  TED has the charter to develop SSD for enterprise customers. More recently, TED has also been tasked to develop SSD controller architecture to support future enterprise SSD designs. We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams across geographically distributed sites to bring innovation to enterprise SSD product road maps.

The candidate will be a key technical member of TED Controller Architecture Team.  He or she will join a team of experts in researching and developing innovative data center/cloud networking, storage, and compute ASIC/FPGA and system solutions. The successful candidate will be engage collaboratively across the company with HW design and verification teams. The primary focus will be on developing, enhancing, and correlating SoC HW architecture for Samsung’s SSD Controller SoC. It includes detail architecture defining with micro-architecture document publish. Ideal candidates should have strong on RTL design and P&R implementation, with expertise in Host interface (e.g, PCIe/NVMe/Gen-Z/CXL/OpenCAPI/Ethernet), CPUs, DRAM, Flash components controllers, cache controllers and interconnect.

We are looking for a SoC HW architect with a passion to develop and document new and innovative ideas and to demonstrate their value and impact.


  • Define detail micro-architecture with other SoC architect
  • Publish micro-architecture document and collaborate with RTL design & verification engineers.
  • Analyze legacy designs for bottlenecks and determine power / performance / reliability / robustness enhancements.
  • Work closely with architects / HW&SW engineers for implementation, integration, and testplan development and execution



  • MS, PhD candidate in EE/CS/CE or 5-10 years of related professional experience
  • Experience of SoC bus, interconnect, CPU, host interface, and memory technologies
  • Experience of VLSI design and verification
  • Experience with high-performance, low power microarchitecture concepts
  • Familiarity with ASIC, computer and embedded system architecture
  • Excellent written and verbal communication, excellent organization skills, and highly self-motivated.
  • Strong working knowledge of RTL design, back-end process for ASIC, verification and P&R implementation.
  • Ability to summarize performance data and communicate issues effectively



  • Excellent scripting and automation of workflows, in C/C++ and/or Python.
  • Experience of storage related project with NVMe, PCIe, and NAND control.
  • Advanced methodology like systemVerilog-OVM or systemVerilog-UVM
  • Statistical analysis
  • Scripting (esp Python / R)


Samsung Semiconductor Inc (SSI), an equal opportunity employer, is a world leader in Memory, System LSI, and LCD technologies. Headquartered in San Jose, California, SSI is a wholly-owned U.S. subsidiary of Samsung Electronics Co., Ltd.- the second largest semiconductor manufacturer in the world and the industry's volume and technology leader in DRAM, NAND Flash, SSDs, mobile DRAM and graphics memory. It is one of the largest providers of system logic, imaging and LED lighting solutions, as well as providing advanced process design and manufacturing for fabless companies. Samsung Semiconductor, Inc. also has a research and innovation center with numerous labs providing product design and research in: logic, memory, image sensors, displays and mobile technologies. In addition, the company supports Samsung Display Company, the largest producer of LCD and OLED displays.

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