ASIC Synthesis/STA Engineer

Engineering - Hardware San Jose, California


Position at Samsung Semiconductor, Inc.


ASIC Synthesis/STA Engineer

Location:San Jose or San Diego


We are looking for a Physical Design Engineer in our San Jose, CA or San Diego, CA location.



· Responsible for hard-macro/full-chip synthesis for next generation multi-mode cellular SOC/connectivity ICs.

· Responsible to lead hard-macro/full-chip timing closure (STA/ timing ECO).

· Responsible to run formal verification for hard-macro/full-chip SOCs.

· Need to work closely with design, DFT and implementation team


· Candidate must have 10+ years latest experience in Synthesis and STA using Synopsys tools.

· Strong timing concepts and experience in leading hard-macro/full-chip timing closure

· Formal verification experience 

· Need to know low power concepts and UPF syntax 

· Good TCL, Perl scripting skills 


• BS with extensive industry experience or MS is preferred.


Samsung Semiconductor Inc (SSI), an equal opportunity employer, is a world leader in Memory, System LSI, and LCD technologies. Headquartered in San Jose, California, SSI is a wholly-owned U.S. subsidiary of Samsung Electronics Co., Ltd.- the second largest semiconductor manufacturer in the world and the industry's volume and technology leader in DRAM, NAND Flash, SSDs, mobile DRAM and graphics memory. It is one of the largest providers of system logic, imaging and LED lighting solutions, as well as providing advanced process design and manufacturing for fabless companies. Samsung Semiconductor, Inc. also has a research and innovation center with numerous labs providing product design and research in: logic, memory, image sensors, displays and mobile technologies. In addition, the company supports Samsung Display Company, the largest producer of LCD and OLED displays.


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