FPGA Design Engineer (4482)
The Central Development Laboratory (CDL) at the National Radio Astronomy Observatory (NRAO) is currently hiring an experienced FPGA design engineer to work on its digital design team. CDL’s digital design team works on cutting-edge projects that provide the critical technology and expertise enabling the next generation of radio astronomy instrumentation. The ideal candidate will be highly proficient in FPGA design, implementation, simulation, and verification at the sub-block and full-chip levels. This position offers an active role in the design of future instrumentation that will reveal the hidden universe such as gravitational waves, the origins or galaxies, the origins of star and planet formation, and black holes.
The selectee will report to the Digital Design Team manager. CDL’s digital design team works cooperatively with other design groups in CDL and across NRAO and other international observatories, so the ideal candidates will be able to effectively research and solve complex technical issues and work with minimal supervision. Because the team often juggles several projects at once, excellent time management skills and ability to multi-task are a must. Strong oral and written communications skills and the ability to document and explain one’s work are also important. A central function of the position relates to the maturing of DSP algorithm designs from simulation to FPGA rapid prototyping platforms, proposing design modifications as needed, and verification efforts with the mindset of developing intellectual property (IP) for design re-use.
The position will be based at the NRAO Central Development Laboratory in Charlottesville, VA, located near the grounds of the University of Virginia (www.virginia.edu). In addition to competitive pay, we provide excellent paid time off benefits (vacation and sick leave). Medical, dental and vision plans are effective on the first day of employment. Our retirement benefit contributes an amount equal to 10 percent of a qualified participant’s base pay. No contribution is required of the employee; we also offer an optional supplemental, tax-deferred plan for employee retirement contributions.
Job Duties Summary
Key duties and responsibilities will include, but not limited to:
- Responsible for Interface Control Documents, Test Plans, Architecture Specifications, Micro-Architecture Specifications, HDL Coding Standards Compliance, and Verification plans.
- Works closely with engineers in NRAO’s Central Development Laboratory and with NRAO astronomers in evaluating and analyzing new concepts, architectures, and implementations.
- Ensures proactive compliance with NRAO and government safety policies and procedures.
- Performs other duties as assigned.
Work is typically performed in a research laboratory environment The successful candidate may be required to travel domestically and internationally by air carrier and to travel by car between NRAO sites.
Bachelor’s degree in electrical engineering.
An advanced degree in electrical engineering or related field.
A minimum of three years’ experience in a related field, which include at least three years FPGA development experience. Candidates with progressively more responsible experience will be considered for a higher-level position ranking.
- Familiarity with Digital Signal Processing concepts and applications
- Experience designing high-speed memory interfaces (DDRx/HBM)
- Experience designing high-speed transceiver protocols (100GbE/400GbE, PCIe, Interlaken)
- Interface standards such as USB, SPI, and I2C
- Scripting in TCL, Python
- Familiarity with timing diagrams, interface specifications, and micro-architecture specifications
- Familiarity with revision control concepts and tools (e.g. Subversion)
- Ability to recognize and clearly report information relevant to s sound FPGA design
- Highly proficient in HDL (Verilog preferred)
- Solid understanding of Xilinx FPGA Development tools (Vivado/SDK)
- Solid understanding of basic digital design concepts (understand how Verilog code translates into logic primitives within a Xilinx FPGA)
- Solid understanding of synthesis, IO placement, floor planning, and Place and-Route (PnR) methodology
- Solid understanding of static timing analysis (STA), design constraints, and the process by which timing closure is achieved in a design
- Detailed understanding of architectural elements within a Xilinx FPGA
- Self-checking testbench development
- Due to export control requirements, this position is open only to United States citizens and US Permanent Residents;
- Occasional travel may be required.
Select the “Apply” button below. Applicants are required to submit a CV/Resume and a cover letter describing interest and suitability for the position. Please upload your CV/Resume with the ‘Add Resume’ button and your cover letter with the ‘Additional Files’ button at the beginning of the application process.
Equal Opportunity Employer Statement
AUI is an equal opportunity employer. Women, Minorities, Vietnam-Era Veterans, Disabled Veterans, Veterans and Individuals with Disabilities are encouraged to apply. To view our complete statement, please visit http://jobs.jobvite.com/nrao/jobs. If you require reasonable accommodation for any part of the application or hiring process due to a disability, you may submit your request by sending an email to firstname.lastname@example.org.
The National Radio Astronomy Observatory is a facility of the National Science Foundation operated under cooperative agreement by Associated Universities, Inc.