Position Description:

Position Summary

The Central Development Laboratory (CDL) at the National Radio Astronomy Observatory (NRAO) is currently hiring an experienced mid-level FPGA design engineer to work on its digital design team. CDL’s digital design team works on cutting-edge projects that provide the critical technology and expertise enabling the next generation of radio astronomy instrumentation. The ideal candidate will be highly proficient in Verilog FPGA design methodology, implementation, simulation, and verification of embedded processor-based FPGA SOC designs. This position offers an active role in the design of future instrumentation that will reveal the hidden universe such as gravitational waves, the origins or galaxies, the origins of star and planet formation, and black holes.

The selectee will report to the Digital Design Team manager. CDL’s digital design team works cooperatively with other design groups in CDL and across the NRAO and other international observatories, so the ideal candidate will be able to effectively research and solve complex technical issues and work with minimal supervision. Because the team often juggles several projects at once, excellent time management skills and ability to multi-task are a must. Strong oral and written communications skills and the ability to document and explain one’s work are also important. A central function of the position relates to the hardware and firmware development of embedded processing sub-systems. Proficiency with the Zynq UltraScale+ MPSoC processing system architecture is mandatory. The selectee will also be responsible for the maturing of DSP algorithm designs from simulation to FPGA rapid prototyping platforms, proposing design modifications as needed, and verification efforts with the mindset of developing intellectual property (IP) for design re-use.

This position will be based at the Central Development Lab (CDL) of the NRAO which is located in Charlottesville, VA. The CDL has a long history of developing new technology to enable forefront research in radio astronomy. Current research and development programs include cryogenic, low-noise front-ends, wideband electromagnetic components such as antenna feeds and polarizers operating from below 1 GHz to nearly 1 THz, phased-array feeds, highly integrated receiver architectures that employ early signal digitization and novel encoding, wideband and scalable digital signal processing architectures, and photonic signal generation, time reference distribution, and data transmission.

In addition to competitive pay, we provide excellent paid time off benefits (vacation and sick leave).  Medical, dental and vision plans are effective on the first day of employment.  Our retirement benefit contributes an amount equal to 10 percent of a qualified participant’s base pay. No contribution is required of the employee; we also offer an optional supplemental, tax-deferred plan for employee retirement contributions.

Position Requirements:

Minimum Education

Bachelor’s degree in electrical engineering.

Minimum Experience

A minimum of 5 years’ detailed digital design experience with processor-based FPGA devices. Candidates with progressively more responsible experience will be considered for a higher-level position ranking.

• Relevant experience with Xilinx Zynq UltraScale+ MPSoC and UltraScale+ Devices
• Experience with Verilog/System Verilog, Xilinx Design Tools (Vivado/Vitas), and Questa Sim

• 5+ years FPGA development experience
• Highly proficient in Verilog

Preferred Experience

• Solid understanding of Xilinx FPGA Development tools (Vivado/Vitas)
• Solid understanding of basic digital design concepts (understand how Verilog code translates into logic primitives within a Xilinx FPGA)
• Solid understanding of synthesis, IO placement, floor planning, and Place and-Route (PnR) methodology
• Solid understanding of static timing analysis (STA), design constraints, and the process by which timing closure is achieved in a design
• Detailed understanding of architectural elements within a Xilinx FPGA
• Self-checking test bench development and TCL scripts
• Mentor Questa Sim

Preferred Qualifications

• Experience designing embedded processor (PS/PL) sub-systems and AXI-4 interfaces
• Experience designing high-speed transceiver protocols (100GbE/400GbE, JESD204B/C, Interlaken)
• Experience with timing diagrams, interface specifications, and micro-architecture specifications
• Experience designing high-speed memory interfaces (DDRx/HBM)
• Experience with interface standards such as USB, SPI, I2C, and PCIe
• Familiarity with Digital Signal Processing concepts and applications
• Familiarity with revision control concepts and tools (e.g. GitHub/GitLab)
• Ability to recognize and clearly report information relevant to a sound FPGA design

Additional Requirements

Occasional travel may be required.

Application Instructions:

Select the “Apply” button. You will need to be prepared to upload your current resume and a cover letter describing interest and suitability for the position.

Equal Opportunity Employer Statement:

AUI is an equal opportunity employer. Women, Minorities, Vietnam-Era Veterans, Disabled Veterans, Veterans and Individuals with Disabilities are encouraged to apply. To view our complete statement, please visit http://jobs.jobvite.com/nrao/jobs. If you require reasonable accommodation for any part of the application or hiring process due to a disability, you may submit your request by sending an email to [email protected]

The National Radio Astronomy Observatory is a facility of the National Science Foundation operated under cooperative agreement by Associated Universities, Inc.

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