IO and ESD Circuit Design Engineer MH-5356
At Cirrus Logic, mixed-signal engineering drives our company. We develop high-performance, low-power signal processing solutions in audio, voice and haptics, delivering innovative end-user experiences and solving difficult challenges for new generations of mobile and consumer devices. While breaking the innovation barrier, weÕve also built an award-winning company culture, thanks to our extraordinary workforce and our ongoing efforts to champion and promote diversity, as well as our principles of equality and fairness in the workplace. Do you enjoy working alongside the industry's top engineers and solving sophisticated challenges for the world's top consumer brands? Join our team and help us continue to make this an exceptional place to work!
The Engineer is responsible for I/O library development, which encompasses the design, simulation, characterization and validation of I/O pad libraries. Also responsible for the definition of the ESD methodology and to specify the chip and IP level ESD requirements. Design ESD protection devices and circuits to meet design requirements. Develop test structures to characterize Si for ESD/LUP properties. Drive the development of design rules based on Si characterization data. Interface with foundry on ESD library and ESD/LUP rule development activities. Engineer needs to have a holistic view of ESD/EOS protection for mixed signal CMOS circuits and the ability to pull pieces together to insure no gaps or blind spots in strategy.
- Design, simulate, and optimize I/O circuits and ESD structures
- Characterization and modeling of I/O libraries to support mixed signal design flow
- Release and maintain I/O libraries and models
- Must understand ESD and latch-up requirements
- Drive ESD sign off methodology for chip & block level projects
- Technical lead capable of pulling together engineer’s, new & existing methodologies to tie ESD-Latchup-IO methodologies together & get buy in from BU’s
- Holistic view of ESD/EOS protection for mixed signal CMOS circuits
- Strong fundamentals in ESD circuit design, layout and testing
- Relevant experience in IO design including CMOS circuit design, ESD and latch-up requirements, physical verification, and characterization
- Chip level ESD signoff experience
- Must understand layout and be able to guide layout engineers
- Proficiency with Cadence schematic capture, layout, and simulation tools
- Ability to work independently and lead or be part of a technical team
- Effective oral and written communication a must
- Experience in IBIS model generation is a plus
This position is located in Austin, TX
Cirrus Logic is an Equal Opportunity/Affirmative Action Employer. We strive to select the best qualified applicant for any opening and to reward employees based on their skills, experience and performance. We do not discriminate on the basis of race, color, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, gender identity, genetic information or any other characteristic protected by law.